While the large-scale integrated circuit (LSI) technology seeks for higher performances, typically to accelerate the data processing speed and to increase the data processing throughput, a number of technologies including lithography have been developed to enable fabrication of finer feature size structures. The sequence of size reduction is known as Moore's law. In the lithography technology, for example, the use of ArF excimer laser exposure has already succeeded in commercial fabrication of 65-nm node devices, and using the immersion lithography, further miniaturization has already been scheduled. However, a possibility is pointed out that a limit will be imposed on the enhancement of performance relying solely on miniaturization, not only from the lithography technology, but also from the technical or material aspect.
Another approach for achieving higher integration density or higher processing speed is to stack LSIs vertically to increase the density of integration or processing speed. This three-dimensional (3D) semiconductor integrated circuit has attracted attention as the technology capable of increasing the density of integration or processing speed independent of the miniaturization of cell structure, and a number of research works have already been made in the art.
The methods of stacking LSIs vertically include a method of joining LSI-bearing wafers together to form a stack, a method of attaching LSI chips on a LSI-bearing wafer to form a stack, and a method of attaching LSI chips one on top of another to form a stack. In these methods, joining LSI chips together is one of key technologies, and the joint is required to be defect-free and rigid.
Joining of LSI chips together may be either direct or indirect joining. The direct method is to join bond surfaces directly, and known as silicon fusion bonding or ion plasma bonding. The direct joining method can generally form a joint of high strength, which does not contain any unnecessary third material in principle, and thus has the advantage of high reliability. On the other hand, the method encounters a high technical hurdle because the bond surfaces are required to have a high flatness and a minimal surface roughness to enable bond formation. In addition, the method is not applicable to ragged surfaces where circuits have already been formed.
Among the indirect methods, the mounting technique of joining chips to form a stack has been commercially utilized, though within a limited range. For example, JP-A 2007-270125 discloses an insulating sheet of thermosetting resin which is used for forming a joint between chips so that a plurality of chips may be stacked.
As an example of forming a joint between wafers, WO 2004059720 (JP-A 2006-522461) discloses a process including building devices on wafers, thinning the wafers, bonding the device-built-in wafers with an insulating material, and forming electrical interconnections between the stacked wafers. The insulating material used is a polyimide material.
It is well known that silicone materials at room temperature have good adhesion to various substrates, and especially excellent adhesion to glass (SiO2) and metals. Silicone rubber has a flexible structure and thermal shock resistance, is effective in bonding metal and/or glass members having different coefficients of thermal expansion, and is used typically as sealant. Silicone rubber is improved in heat resistance by incorporating phenyl or similar groups so that it may be used at relatively high temperatures, but the temperature limit is about 300° C. The reason is that the dialkylsiloxane moiety which is a main constituent of silicone rubber is subject to thermal isomerization into a dialkyl cyclic which is decomposed and scattered away. On the other hand, siloxane or silica resins obtained through dehydrolytic condensation of tri- or tetra-functional hydrolyzable silanes free of a dialkylsiloxane moiety such as trialkoxysilanes and tetraalkoxysilanes do not undergo thermal decomposition or degradation, but have a rigid and brittle structure so that cracks readily occur if the coefficient of thermal expansion differs between the resin and the substrate. These resins are thus difficult to form a satisfactory film by thermosetting.
In conjunction with 3D semiconductor devices and 3D sensors as mentioned above, a manufacturing process including joining substrates via a bond layer and then processing the substrate assembly is contemplated in order to enable fabrication of more complex devices. Nevertheless, the manufacturing process may include treatment at high temperatures of 400° C. or higher, for example, CVD step. If the substrate assembly having a plurality of substrates joined through a bond layer is treated at such high temperatures of 400° C. or higher, most organic bonding agents lose their bond strength. There is thus a desire to have a bonding agent having a low modulus of elasticity and resistance to high temperatures.
Although bonding agents or adhesives having satisfactory high-temperature resistance so that they may be used at or above 1000° C. are limited to inorganic ones, some bonding agents to be used at high temperatures in the range of 400° C. to 500° C. contain an organic silicone compound as one component. For example, JP-A H02-180965 discloses an adhesive agent for use around an exhaust gas conduit from an engine, which comprises a silicone compound as a component capable of binding the main adhesive component, inorganic material. JP-A 2008-14716 describes an inorganic sodium silicate-based adhesive agent as the heat resistant adhesive agent for optical fibers, wherein upon heating, stresses are applied to the fibers to give rise to an accident that cracks form, but such stresses may be mitigated by adding polymethylsilsesquioxane particles having a particle size of 2 μm. These adhesive agents take advantage of the high-temperature resistance of Si—O—Si linkage of polysiloxane materials although they cannot be a precise bonding agent to be used in the interior of semiconductor devices.
However, as discussed in JP-A 2008-14716, inorganic adhesive agents having good high-temperature resistance have so high a hardness that a problem arises when thermal stresses are applied, and are difficult to use in semiconductor and similar systems where the presence of sodium and potassium ions should be avoided. The approach for stress mitigation using macroscopic particles is hesitatingly employed in the application where the adhesive is used as a thin film or a high flatness is required during coating.
When the silicone compounds containing many divalent silicon atoms (which refer to a silicon atom having bonds to two oxygen atoms) as described in JP-A H02-180965 are used in an environment which will reach temperatures as high as 400° C., disproportionation reaction occurs in some siloxane moieties to form cyclic siloxanes which are liberated. Then, if such a material is used as the main component of the bond layer, an accident occurs that the bond strength is gradually lost or the gas liberated can interfere with the function of semiconductor.
The above and other patent documents, which are incorporated herein by reference, are listed below.